1. Field of the Invention
The present invention relates generally to semiconductor device fabrication technology and techniques for improving the performance of semiconductor devices. Specifically, the present invention relates to implementing sacrificial materials to enhance the performance of semiconductor devices.
2. Description of the Related Art
As is well known, the semiconductor industry is moving toward implementing larger substrates having higher density with devices having smaller features. To achieve this task, millions of transistors are connected through multiple layers of interconnect metallization lines, insulating dielectric layers, and conductive via structures and are fabricated on a wafer substrate. Originally, metallization lines and vias were predominantly formed from aluminum, as it is relatively inexpensive, easy to etch, and has relatively low resistivity, while insulators were made predominantly from silicon dioxide. However, due to the decrease in the size of the device features, vias and contact holes as well as the distance between the metallization lines in conjunction with system-on-chip evolution, there is an increased demand to improve semiconductor device performance through changing the materials implemented in semiconductor fabrication. So far, this has been a two-fold task.
First, rather than aluminum, copper interconnect lines, vias, and contact holes are being implemented. Replacing of aluminum with copper has been favorable, as the latter has lower resistivity and better conductivity and electromigration properties than the former. However, replacing aluminum with copper has been problematic, as it mandates a fundamental change in the metal interconnect formation. Specifically, while aluminum interconnects are formed by etching out unprotected portions of the thin aluminum film overlaid on the surface of the substrate, copper interconnects are formed through depositing copper into via holes and trenches that are etched into dielectric layers. As a result, in a semiconductor device having copper interconnects, a planarization operation must be performed on the substrate surface so as to remove overburden copper from non-trench, via or contact plug areas of the dielectric.
Second, instead of silicon dioxide, dielectric materials with low dielectric permittivity, or so-called low-K dielectric materials, are being used as insulators. Low-K dielectric materials are preferred because first, they reduce interconnect-to-interconnect capacitance, as the coupling capacitance between two metallization lines placed in close proximity of each other is directly proportional to the dielectric constant of the insulating dielectric material used. Second, low-K dielectric materials reduce cross-talk noise, since the lower is the dielectric constant of a dielectric, the lower is the possibility of cross-metallization line signal interference. By way of example, while the predominantly used dielectric, silicon dioxide, has a dielectric constant of about 4.0, air has the lowest dielectric constant of 1.0, and other low-K dielectric materials ranging from about 1.5 and about 3.5. As air has been recognized to have the lowest dielectric constant, there has been a trend in the semiconductor fabrication technology to manufacture dielectric materials with dielectric constants close to that of air.
So far, such attempts have resulted in producing highly porous dielectric materials. However, the poor mechanical strength of such porous dielectric materials as well as the current state of the semiconductor fabrication technology hinders their implementation in the semiconductor fabrication process. Particularly, the poor mechanical strength of low-K dielectric materials is problematic during the chemical mechanical planarization (CMP) operation performed on copper metallization lines. As is well known, in a CMP operation, the substrate surface is applied onto a moving polishing pad with force, thus removing the overburden metal from over the substrate surface. However, performing a CMP operation on a semiconductor device having porous low-K dielectric material is complicated as the application of the substrate surface onto the polishing pad may cause regions of the semiconductor structure to collapse or crack, thus hindering performance or requiring that the fabricated semiconductor wafer be discarded. As can be appreciated, when these problems are introduced during semiconductor fabrication processes, the yield of good chips can dramatically decrease, in addition to reducing wafer throughput.
In view of the foregoing, a need exists for semiconductor structures that can be fabricated using conventional techniques that provide good structural support during CMP operations, while still producing devices having low capacitive delays such as those implementing low-K dielectric materials.